Optimizing Schottky S/D offset for 25-nm dual-gate CMOS performance

Author

Connelly, Daniel ; Faulkner, Carl ; Grupp, D.E.

Author_Institution

Acorn Technol., Palo Alto, CA, USA

Volume

24

Issue

6

fYear

2003

fDate

6/1/2003 12:00:00 AM

Firstpage

411

Lastpage

413

Abstract

For the first time, mixed mode simulation is used to optimize the design of ultrathin-body dual-gate metal source/drain 25-nm CMOS, showing an advantage for source/drain-to-gate underlap, rather than overlap. The effect of source/drain workfunction and silicon thickness on the optimal underlap, and on the resulting circuit speed, is examined. A substantial performance advantage versus doped source/drain is demonstrated.

Keywords

CMOS integrated circuits; MOSFET; circuit optimisation; circuit simulation; semiconductor device models; work function; 25 nm; 25-nm dual-gate CMOS performance; NFET parameters; PFET parameters; Schottky S/D offset optimization; circuit speed; mixed mode simulation; performance advantage; semiconductor device modeling; silicon thickness; source/drain work function; source/drain-to-gate underlap; ultrathin-body dual-gate metal source/drain CMOS; Circuit simulation; Design optimization; Doping; MOS devices; Reflection; Schottky barriers; Semiconductor device modeling; Semiconductor process modeling; Silicon on insulator technology; Threshold voltage;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/LED.2003.813363

Filename

1213873