Integrated stereo ΔΣ class D amplifier

Author

Gaalaas, Eric ; Liu, Bill Yang ; Nishimura, Naoaki ; Adams, Robert ; Sweetland, Karl

Author_Institution

Analog Devices Inc., Wilmington, MA, USA

Volume

40

Issue

12

fYear

2005

Firstpage

2388

Lastpage

2397

Abstract

A 2×40 W class D amplifier chip is realized in 0.6-μm BCDMOS technology, integrating two delta-sigma (ΔΣ) modulators and two full H-bridge switching output stages. Analog feedback from H-bridge outputs helps achieve 67-dB power supply rejection ratio, 0.001% total harmonic distortion, and 104-dB dynamic range. The modulator clock rate is 6 MHz, but dynamically adjusted quantizer hysteresis reduces output data rate to 450 kHz, helping achieve 88% power efficiency. At AM radio frequencies, the modulator output spectrum contains a single peak, but is otherwise tone-free, unlike conventional pulse-width modulation (PWM) modulators which contain energetic tones at harmonics of the PWM clock frequency.

Keywords

BIMOS integrated circuits; HF amplifiers; delta-sigma modulation; harmonic distortion; 0.6 micron; 104 dB; 40 W; 450 kHz; 6 MHz; 67 dB; AM radio frequency; BCDMOS technology; H-bridge output; analog feedback; class D amplifier chip; delta-sigma modulator; modulator clock rate; modulator output spectrum; power supply rejection ratio; quantizer hysteresis; sigma-delta modulation; switching amplifiers; total harmonic distortion; Clocks; Delta modulation; Dynamic range; Frequency modulation; Hysteresis; Output feedback; Power supplies; Pulse width modulation; Radio frequency; Total harmonic distortion; Sigma-delta modulation; switching amplifiers;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2005.856266

Filename

1546215