• DocumentCode
    746921
  • Title

    Multilevel-Huffman Test-Data Compression for IP Cores With Multiple Scan Chains

  • Author

    Kavousianos, Xrysovalantis ; Kalligeros, Emmanouil ; Nikolos, Dimitris

  • Author_Institution
    Dept. of Comput. Sci., Ioannina Univ., Ioannina
  • Volume
    16
  • Issue
    7
  • fYear
    2008
  • fDate
    7/1/2008 12:00:00 AM
  • Firstpage
    926
  • Lastpage
    931
  • Abstract
    Various compression methods have been proposed for tackling the problem of increasing test-data volume of contemporary, core-based systems. Despite their effectiveness, most of the approaches that are based on classical codes (e.g., run-lengths, Huffman) cannot exploit the test-application-time advantage of multiple-scan-chain cores, since they are not able to perform parallel decompression of the encoded data. In this paper, we take advantage of the inherent parallelism of Huffman decoding and we present a generalized multilevel Huffman-based compression approach that is suitable for cores with multiple scan chains. The size of the encoded data blocks is independent of the slice size (i.e., the number of scan chains), and thus it can be adjusted so as to maximize the compression ratio. At the same time, the parallel data-block decoding ensures the exploitation of most of the scan chains´ parallelism. The proposed decompression architecture can be easily modified to suit any Huffman-based compression scheme.
  • Keywords
    Huffman codes; block codes; data compression; decoding; logic testing; system-on-chip; Huffman decoding; IP cores; core-based systems; decompression architecture; generalized multilevel-Huffman test-data compression; multiple scan chain parallelism; parallel data-block decoding; system-on-a-chip testing; Decoding; Digital systems; Encoding; Intellectual property; Parallel processing; Performance evaluation; System testing; Test data compression; Test pattern generators; Time to market; Huffman encoding; test data compression;
  • fLanguage
    English
  • Journal_Title
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1063-8210
  • Type

    jour

  • DOI
    10.1109/TVLSI.2008.2000448
  • Filename
    4539810