A Fully Pipelined Architecture for the LOCO-I Compression Algorithm

This paper presents the design of a novel architectural implementation of the LOCO-I compression scheme, the lossless/near-lossless algorithm used inside the JPEG-LS standard. Differently from what previously reported in literature, the proposed design fully exploits the sequential nature of the algorithm by means of a pipelined architecture, without modifications to the original compression scheme. The result is a good performance circuit well fitted for field-programmable gate-array realization, thus devised for application in the wearable computers and remote sensing domains.