Advanced integrated-circuit reliability simulation including dynamic stress effects

Author

Hsu, Wen-jay ; Sheu, Bing J. ; Gowda, Sudhir M. ; Hwang, Chang-Gyu

Author_Institution

Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA

Volume

27

Issue

3

fYear

1992

fDate

3/1/1992 12:00:00 AM

Firstpage

247

Lastpage

257

Abstract

A systematic approach to predict semiconductor degradation effects using reliability simulation is described. The DC degradation monitor is first extracted during transient circuit simulation. An AC degradation factor is then used to determine circuit performance degradation. By using these techniques on the design of CMOS components, proper long-term reliability can be achieved for high-speed circuits. Experimental results on digital circuits using an industrial submicrometer technology demonstrate the effectiveness of this approach in reliable VLSI circuit design. Results on two-input NAND gates, DRAM precharging circuit, and SRAM control circuits are presented

Keywords

VLSI; circuit analysis computing; circuit reliability; digital integrated circuits; digital simulation; integrated circuit technology; monolithic integrated circuits; AC degradation factor; CMOS components; DC degradation monitor; DRAM precharging circuit; SRAM control circuits; VLSI circuit design; circuit performance degradation; digital circuits; dynamic stress effects; high-speed circuits; integrated-circuit; long-term reliability; reliability simulation; submicrometer technology; transient circuit simulation; two-input NAND gates; CMOS technology; Circuit optimization; Circuit simulation; Degradation; Digital circuits; Integrated circuit reliability; Monitoring; Predictive models; Random access memory; Semiconductor device reliability;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.121545

Filename

121545