• DocumentCode
    751801
  • Title

    A fast VLSI-efficient self-routing permutation network

  • Author

    Cam, Hasan ; Fortes, Jose A B

  • Author_Institution
    Dept. of Comput. Eng., King Fahd Univ. of Pet. & Miner., Dhahran, Saudi Arabia
  • Volume
    44
  • Issue
    3
  • fYear
    1995
  • fDate
    3/1/1995 12:00:00 AM
  • Firstpage
    448
  • Lastpage
    453
  • Abstract
    A multistage self-routing permutation network is presented. This network is constructed from concentrators and digit-controlled 2×4 switches. A destination-tag routing scheme is used to realize any arbitrary permutation. The network has O(log2 N) gate-delay and uses O(N2) VLSI-area, where N is the number of inputs. Assuming packet-switching is used for message transmission, the delay and VLSI-area of the network are smaller than those of any self-routing permutation network presented to date
  • Keywords
    VLSI; computational complexity; multiprocessor interconnection networks; parallel algorithms; concentrators; delay; destination-tag routing scheme; digit-controlled switches; fast VLSI-efficient self-routing permutation network; gate-delay; packet-switching; Computational modeling; Computer networks; Corporate acquisitions; Costs; Genetic mutations; Intelligent networks; Multiprocessor interconnection networks; Routing; Sorting; Switches;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/12.372036
  • Filename
    372036
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=751801