DocumentCode
754612
Title
Logic Minimization and Testability of 2-SPP Networks
Author
Bernasconi, Anna ; Ciriani, Valentina ; Drechsler, Rolf ; Villa, Tiziano
Author_Institution
Dept. of Comput. Sci., Univ. of Pisa, Pisa
Volume
27
Issue
7
fYear
2008
fDate
7/1/2008 12:00:00 AM
Firstpage
1190
Lastpage
1202
Abstract
The 2-SPP networks are three-level EXOR-AND-OR forms, with EXOR gates being restricted to fan-in 2. This paper presents a heuristic algorithm for the synthesis of these networks in a form that is fully testable in the stuck-at fault model (SAFM). The algorithm extends the EXPAND-IRREDUNDANT-REDUCE paradigm of ESPRESSO in heuristic mode, and it iterates local minimization and reshape of a solution until no further improvement can be achieved. This heuristic could escape from local minima using a LAST_GASP-like procedure. Moreover, the testability of 2-SPP networks under the SAFM is studied, and the notion of EXOR-irredundancy is introduced to prove that the computed 2-SPP networks are fully testable under the SAFM. Finally, this paper reports a large set of experiments showing high-quality results with affordable run times, handling also examples whose exact solutions could not be computed.
Keywords
logic gates; logic testing; 2-SPP network testing; expand-irredundant-reduce paradigm; heuristic algorithm; logic minimization; stuck-at fault model; three-level EXOR-AND-OR form; Computer networks; Computer science; Heuristic algorithms; Information technology; Logic testing; Minimization methods; Network synthesis; Robustness; Logic synthesis; testing; three-level logic networks;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/TCAD.2008.923072
Filename
4544853
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