Inductance and Coupling of Stacked Vias in a Multilayer Superconductive IC Process

With many advanced superconductive integrated circuit fabrication processes now moving to multiple ground/shield layers and buried signal lines, and gate dimensions shrinking, the inductance of stacked vias becomes significant. Analytical and two-dimensional inductance calculation methods cannot account for stacked via inductance. Here we show experimental test structures devised to verify the calculated inductance of stacked vias with the three-dimensional utility InductEx. The structures are manufactured in the AIST 9-layer ADP2 process, and are measured through SQUID modulation. We discuss the effects of the absence of ground sleeves around the vias on return current paths and inductance, as well as the coupling between stacked vias in close proximity, and present experimental results. Finally we examine the reliability of calculations with InductEx for such via structures.