High-speed performance of 0.35 μm CMOS gates fabricated on low-dose SIMOX substrates with/without an N-well underneath the buried oxide layer

Author

Yoshino, A. ; Kumagai, K. ; Hamatake, N. ; Tatsumi, T. ; Onishi, H. ; Kurosawa, Shunsuke ; Okumura, K.

Author_Institution

ULSI Device Dev. Lab., NEC Corp., Kanagawa, Japan

Volume

17

Issue

3

fYear

1996

fDate

3/1/1996 12:00:00 AM

Firstpage

106

Lastpage

108

Abstract

We present experimental results concerning the propagation delay time of the 0.35 μm CMOS gate chains (inverter, 3NAND, and 3NOR) fabricated on low-dose SIMOX substrates with and without the N-well formed underneath the buried oxide layer in the PMOS region. Using such experimental data as the capacitance voltage characteristics of the buried oxide layer, and the enhanced PMOS transistor drivability due to the negative back bias effect, we clarify the most essential factor of the high-speed performance of the CMOS/SIMOX circuits fabricated on a low-dose SIMOX substrate.

Keywords

CMOS logic circuits; SIMOX; buried layers; logic gates; 0.35 micron; 3NAND; 3NOR; CMOS gates; N-well; PMOS transistor drivability; buried oxide layer; capacitance voltage characteristics; high-speed circuits; inverter; low-dose SIMOX substrates; negative back bias; propagation delay time; Capacitance measurement; Capacitance-voltage characteristics; Circuits; Laboratories; MOSFETs; Parasitic capacitance; Propagation delay; Silicon; Substrates; Time measurement;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/55.485182

Filename

485182