Efficient implementation techniques for gracefully degradable multiprocessor systems

We propose the dynamic reconfiguration network (DRN) and a monitoring-at-transmission (MAT) bus to support dynamic reconfiguration of an N-modular redundancy multiprocessor system. In the reconfiguration process, a maximal number of processor triads are guaranteed to be formed on each processor cluster, thus supporting gracefully degradable operations. This is made possible by dynamically routing the control and clock signals of processors on the DRN so as to synchronize fault-free processors. The MAT bus is an efficient way to implement a triple modular redundant pipeline voter, which is a special case of the voting network proposed by Parhami (1991). Extensive experimental results have shown to support our design concept, and the performance of different cache memory organizations is evaluated through an analytic model