Switch-level fault detection and diagnosis environment for MOS digital circuits using spectral techniques

A switch-level fault detection and diagnosis environment for MOS digital circuits using a compression data method based on a spectral signature is described. The selected fault model includes an MOS transistor permanently On and Off, breaks in internal gate lines, and shorts between two internal nodes of different logic gates, or between the internal nodes within the same complex gate. Circuit editing is performed in modules containing simple switch-level descriptions of the transistors. From the module structure a fault list is created, which will later be processed to eliminate all equivalent faults (fault collapsing). Simulation of the faults contained in this lift, and Walsh or Haar spectral analysis of the outputs, allow a data file to be created, containing a list of faults detected, a list of diagnosed fault groups and the spectral signature for each of these groups. The circuits are tested by comparing the information contained in this file and the data provided by a logic analysis system (LAS).