DocumentCode
763007
Title
Design of a low-power 10 Gb/s Si bipolar 1:16-demultiplexer IC
Author
Lao, Zhihao ; Langmann, Ulrich
Author_Institution
Mikroelektronik Zentrum, Ruhr-Univ., Bochum, Germany
Volume
31
Issue
1
fYear
1996
fDate
1/1/1996 12:00:00 AM
Firstpage
128
Lastpage
131
Abstract
The design of a low-power Si bipolar 1:16-demultiplexer IC built of 1:4-demultiplexer subcomponents for 10 Gb/s (STM-64) is described. The 1:4-demultiplexers feature an architecture with low component count. Special latches controlled by two clock voltages are used. The 1:16-demultiplexer operates up to 12.5 Gb/s with a power dissipation of only 1.5 W at a single power supply voltage of -3 V
Keywords
bipolar digital integrated circuits; demultiplexing equipment; integrated circuit design; silicon; 1.5 W; 10 Gbit/s; 1:4-demultiplexer subcomponents; 3 V; STM-64; Si; design; latches; low-power Si bipolar 1:16-demultiplexer IC; Bipolar integrated circuits; Clocks; Communication system control; Energy consumption; Latches; Power dissipation; SONET; Switches; Synchronous digital hierarchy; Voltage control;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/4.485875
Filename
485875
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