A high-speed low-power tri-state driver flip flop for ultra-low supply voltage GaAs heterojunction FET LSI´s

Author

Maeda, Tadashi ; Numata, Keiichi ; Tokushima, Masatoshi ; Ishikawa, Masaoki ; Fukaishi, Muneo ; Hida, Hikam ; Ohno, Yasuo

Author_Institution

Microelectron. Res. Lab., NEC Corp., Ibaraki, Japan

Volume

31

Issue

2

fYear

1996

fDate

2/1/1996 12:00:00 AM

Firstpage

240

Lastpage

246

Abstract

This paper describes a low-supply-voltage flip flop circuit design. The advantages of low supply voltage are discussed. Based on an analytical circuit delay model, conventional flip flop operating speed degradation below 1 V supply voltage is analyzed. We then propose a new GaAs static flip flop, called TD-FF (tri-state driver flip-flop), for ultra-low supply voltage GaAs heterojunction FET LSIs. The TD-FF operates at a data rate of 10 Gbps with 18 mW power consumption at 0.8 V supply voltage, which is 1/5 of the minimum value reported for D-FFs so far. We also demonstrate a 1/8 static frequency divider IC using the TD-FF configuration. This IC operates up to 10 GHz with 38 mW at 0.8 V supply voltage

Keywords

III-V semiconductors; delays; direct coupled FET logic; field effect logic circuits; flip-flops; frequency dividers; gallium arsenide; large scale integration; logic design; 0.8 V; 10 GHz; 10 Gbit/s; 18 mW; 38 mW; GaAs; GaAs static flip flop; analytical circuit delay model; heterojunction FET; high-speed low-power flip flop; static frequency divider IC; tri-state driver flip flop; ultra-low supply voltage; Analytical models; Circuit analysis; Circuit synthesis; Degradation; Delay; Driver circuits; Flip-flops; Gallium arsenide; Heterojunctions; Low voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.488001

Filename

488001