A Scalable Packet Sorting Circuit for High-Speed WFQ Packet Scheduling

Author

McLaughlin, K. ; Sezer, S. ; Blume, H. ; Yang, X. ; Kupzog, F. ; Noll, T.

Author_Institution

Inst. of Electron., Queen´´s Univ. Belfast, Belfast

Volume

16

Issue

7

fYear

2008

fDate

7/1/2008 12:00:00 AM

Firstpage

781

Lastpage

791

Abstract

A novel implementation of a tag sorting circuit for a weighted fair queueing (WFQ) enabled Internet protocol (IP) packet scheduler is presented. The design consists of a search tree, matching circuitry, and a custom memory layout. It is implemented using 130-nm silicon technology and supports quality of service (QoS) on networks at line speeds of 40 Gb/s, enabling next generation IP services to be deployed.

Keywords

Internet; computer network management; quality of service; transport protocols; tree searching; Internet protocol packet scheduler; Si; high-speed WFQ packet scheduling; matching circuitry; next generation IP services; quality of service; scalable packet sorting circuit; search tree; size 130 nm; tag sorting circuit; weighted fair queueing; Circuits; Delay; Hardware; Internet; Job shop scheduling; Quality of service; Scheduling algorithm; Silicon; Sorting; Traffic control; Internet packet scheduling; lookup; quality of service (QoS); time-stamp sorting; traffic management; weighted fair queueing (WFQ);

fLanguage

English

Journal_Title

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Publisher

ieee

ISSN

1063-8210

Type

jour

DOI

10.1109/TVLSI.2008.2000323

Filename

4553746