• DocumentCode
    7765
  • Title

    A Multicast Tree Router for Multichip Neuromorphic Systems

  • Author

    Merolla, P. ; Arthur, John ; Alvarez, R. ; Bussat, Jean-Marie ; Boahen, K.

  • Author_Institution
    Stanford Univ., Stanford, CA, USA
  • Volume
    61
  • Issue
    3
  • fYear
    2014
  • fDate
    Mar-14
  • Firstpage
    820
  • Lastpage
    833
  • Abstract
    We present a tree router for multichip systems that guarantees deadlock-free multicast packet routing without dropping packets or restricting their length. Multicast routing is required to efficiently connect massively parallel systems´ computational units when each unit is connected to thousands of others residing on multiple chips, which is the case in neuromorphic systems. Our tree router implements this one-to-many routing by branching recursively-broadcasting the packet within a specified subtree. Within this subtree, the packet is only accepted by chips that have been programmed to do so. This approach boosts throughput because memory look-ups are avoided enroute, and keeps the header compact because it only specifies the route to the subtree´s root. Deadlock is avoided by routing in two phases-an upward phase and a downward phase-and by restricting branching to the downward phase. This design is the first fully implemented wormhole router with packet-branching that can never deadlock. The design´s effectiveness is demonstrated in Neurogrid, a million-neuron neuromorphic system consisting of sixteen chips. Each chip has a 256 × 256 silicon-neuron array integrated with a full-custom asynchronous VLSI implementation of the router that delivers up to 1.17 G words/s across the sixteen-chip network with less than 1 μs jitter.
  • Keywords
    VLSI; broadcasting; elemental semiconductors; microprocessor chips; multicast communication; multiprocessor interconnection networks; neural nets; silicon; telecommunication network routing; Neurogrid; Si; asynchronous VLSI implementation; computational units; deadlock-free multicast packet routing; downward phase; header compact; memory look-ups; million-neuron neuromorphic system; multicast tree router; multichip neuromorphic systems; one-to-many routing; packet branching; packet broadcasting; silicon-neuron array; subtree root; upward phase; wormhole router; Arrays; Neuromorphics; Neurons; Random access memory; Routing; System recovery; Unicast; Asynchronous; VLSI; deadlock; multicast; neuromorphic; router; tree network;
  • fLanguage
    English
  • Journal_Title
    Circuits and Systems I: Regular Papers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1549-8328
  • Type

    jour

  • DOI
    10.1109/TCSI.2013.2284184
  • Filename
    6678321