• DocumentCode
    780935
  • Title

    Sub-30-nm FUSI CMOS Transistors Fabricated by Simple Method Without Additional CMP Process

  • Author

    Fukutome, Hidenobu ; Hosaka, Kimihiko ; Kawamura, Kazuo ; Ohta, Hiroyuki ; Uchino, Yasunori ; Akiyama, Shinichi ; Aoyama, Takayuki

  • Author_Institution
    Fujitsu Labs. Ltd., Tokyo
  • Volume
    29
  • Issue
    7
  • fYear
    2008
  • fDate
    7/1/2008 12:00:00 AM
  • Firstpage
    765
  • Lastpage
    767
  • Abstract
    We fabricated sub-30-nm fully silicide (FUSI) CMOS transistors by a simple method without additional chemical-mechanical-polish and gate-capping-layer processes. The FUSI draped with source/drain (S/D) capping layer (D-FUSI) featuring shallow S/D Ni silicided layer without modulation of geometric structures is suitable to improve electrical characteristics of the short-channel transistor. Drive currents of 25-nm D-FUSI CMOS transistors increased by 15% more than those of the control.
  • Keywords
    CMOS integrated circuits; transistors; drive currents; electrical characteristics; fully silicide CMOS transistors; short-channel transistor; source-drain capping layer; sub30-nm FUSI CMOS transistors; CMOS process; CMOS technology; Chemical processes; Electric variables; Etching; Fabrication; Impurities; MOSFETs; Protection; Silicides; CMOS; fully silicide (FUSI);
  • fLanguage
    English
  • Journal_Title
    Electron Device Letters, IEEE
  • Publisher
    ieee
  • ISSN
    0741-3106
  • Type

    jour

  • DOI
    10.1109/LED.2008.2000915
  • Filename
    4558110
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=780935