A 100 MHz 2-D 8×8 DCT/IDCT processor for HDTV applications

Author

Madisetti, Avanindra ; Willson, Alan N., Jr.

Author_Institution

Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA

Volume

5

Issue

2

fYear

1995

fDate

4/1/1995 12:00:00 AM

Firstpage

158

Lastpage

165

Abstract

This paper discusses the design of a combined DCT/IDCT CMOS integrated circuit for real time processing of HDTV signals. The processor operates on 8×8 blocks. Inputs include the blocked pixels that are scanned one pixel at a time, and external control signals that control the forward or inverse modes of operation. Input pixels have a precision of 9-b for the DCT and 12-b for the IDCT. The layout has been generated with a 0.8 μm CMOS library using the Mentor Graphics GDT tools and measures under 10 mm². Critical path simulation indicates a maximum input sample rate of 100 MHz

Keywords

CMOS digital integrated circuits; circuit layout CAD; discrete cosine transforms; high definition television; integrated circuit layout; inverse problems; transform coding; video coding; 0.8 micron; 100 MHz; 12 bit; 64 pixel; 8 pixel; 9 bit; CMOS integrated circuit; CMOS library; DCT/IDCT processor; HDTV applications; Mentor Graphics GDT tools; blocked pixels; critical path simulation; external control signals; input pixels; maximum input sample rate; real time processing; transform coding; video coding; CMOS integrated circuits; Clocks; Costs; Discrete cosine transforms; HDTV; Layout; Matrix decomposition; Signal design; Signal processing; Transform coding;

fLanguage

English

Journal_Title

Circuits and Systems for Video Technology, IEEE Transactions on

Publisher

ieee

ISSN

1051-8215

Type

jour

DOI

10.1109/76.388064

Filename

388064