DocumentCode
789396
Title
The study of threshold voltage extraction of nitride spacer NMOS transistors in early stage hot carrier stress
Author
Tsai, Jun-Lin ; Huang, Kai-Ye ; Lai, Jinn-Horng ; Gong, Jeng ; Yang, Fu-Jei ; Lin, Sun-Yun
Author_Institution
Inst. of Electron. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Volume
49
Issue
8
fYear
2002
fDate
8/1/2002 12:00:00 AM
Firstpage
1488
Lastpage
1490
Abstract
Threshold voltage Vt extracted by gm-maximum extrapolation method under early stage hot carrier stress is proven to be an inappropriate method once electrons are trapped in a nitride spacer. The trapping of electrons in a nitride spacer increases the series drain resistance, reducing the transconductance gm and the corresponding gate-to-source voltage Vgs at which peak gm occurs. It ultimately decreases the threshold voltage Vt extracted by the gm-maximum extrapolation method. A novel algorithm is derived to determine the relationship between the measured data and the true threshold voltage of such a device under hot carrier stress by considering the effect of series resistance in gm-maximum extrapolation method.
Keywords
MOSFET; extrapolation; hot carriers; interface states; semiconductor device models; early stage hot carrier stress; maximum extrapolation method; nitride spacer NMOS transistors; reverse bias stress; series drain resistance; shallow trench isolation; threshold voltage extraction; time dependence; transconductance; true threshold voltage; Charge carrier processes; Data mining; Degradation; Electron traps; Extrapolation; Hot carriers; MOS devices; MOSFET circuits; Stress measurement; Threshold voltage;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/TED.2002.801438
Filename
1019938
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