Transforming bit-serial communication circuits into fast parallel VLSI implementations

Author

Lewis, David M. ; Thomson, Brian W. ; Boulton, Peter I P ; Lee, E. Stewart

Author_Institution

Dept. of Electr. Eng., Toronto Univ., Ont., Canada

Volume

23

Issue

2

fYear

1988

fDate

4/1/1988 12:00:00 AM

Firstpage

549

Lastpage

557

Abstract

Bit-serial circuits are traditionally used to encode, decode, and perform error checking in digital communication and mass storage systems. The throughput of these circuits can form a bottleneck in system performance. Expensive technology may be required to match the speed of the rest of the system. Techniques for transforming these circuits into bit-parallel implementations which achieve high throughput are presented. Circuits designed for a 50-Mb/s local area network controller are used as examples. Coding, decoding, and cyclical redundancy check circuits are fabricated in 4-μm CMOS, yet achieve 50-Mb/s bandwidth

Keywords

CMOS integrated circuits; VLSI; decoding; encoding; local area networks; 4 micron; 50 Mbit/s; CMOS; bandwidth; bit-parallel implementations; bit-serial communication circuits; cyclical redundancy check circuits; digital communication; error checking; fast parallel VLSI implementations; local area network controller; mass storage systems; throughput; Bandwidth; CMOS technology; Circuits; Clocks; Communication system control; Cyclic redundancy check; Cyclic redundancy check codes; Decoding; Digital communication; Local area networks; Logic; System performance; Throughput; Very large scale integration;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.1021

Filename

1021