• DocumentCode
    792566
  • Title

    Elevated field insulator (ELFIN) process for device isolation of ultrathin SOI MOSFETs with top silicon film less than 20 nm

  • Author

    Jong-Wook Lee ; Saitoh, Y. ; Koh, R. ; Mogami, T.

  • Author_Institution
    Silicon Syst. Res. Labs., NEC Co., Kanagawa, Japan
  • Volume
    23
  • Issue
    8
  • fYear
    2002
  • Firstpage
    467
  • Lastpage
    469
  • Abstract
    New device isolation process, called elevated field insulator (ELFIN) process, for ultrathin SOI devices with top silicon film less than 20 nm has been proposed and successfully demonstrated. In ELFIN process, gate oxidation and subsequent gate poly-Si deposition is followed by conventional STI process. ELFIN process has a field region elevated compared with active silicon region, leading to prevention of silicon edge from being wrapped around by gate poly-Si. It is found that thin-film SOI NMOSFETs with ELFIN process have better reverse narrow channel effect about 50% at W/sub G/=0.3 μm than that with conventional shallow trench isolation (STI) process.
  • Keywords
    MOSFET; isolation technology; oxidation; silicon-on-insulator; transmission electron microscopy; NMOSFET; Si-SiO/sub 2/; cross-sectional TEM; device isolation process; elevated field insulator process; gate oxidation; gate patterning; gate polysilicon deposition; perfect ideal isolation; process sequence; reverse narrow channel effect; shallow trench isolation; thin top silicon film; trench gap-filling; ultrathin SOI MOSFET; Dielectric thin films; Insulation; MOSFETs; Oxidation; Semiconductor films; Semiconductor thin films; Silicon on insulator technology; Thin film circuits; Thin film devices; Transistors;
  • fLanguage
    English
  • Journal_Title
    Electron Device Letters, IEEE
  • Publisher
    ieee
  • ISSN
    0741-3106
  • Type

    jour

  • DOI
    10.1109/LED.2002.801281
  • Filename
    1021095