Pipelined delay-sum architecture based on bucket-brigade devices for on-chip ultrasound beamforming

Author

Mo, Yaowu ; Tanaka, Tsunehisa ; Arita, Shigeru ; Tsuchitani, Akira ; Inoue, Koji ; Suzuki, Yoshihiko

Author_Institution

Technol. Res. Inst. of Osaka Prefecture, Japan

Volume

38

Issue

10

fYear

2003

Firstpage

1754

Lastpage

1757

Abstract

A pipelined delay-sum architecture based on bucket-brigade devices is proposed as an analog beamformer for integrated far-field steering scanning of a micromachined piezoelectric ultrasonic sensor phased array. The prototype beamformer, fabricated with an 8-μm standard CMOS process, exhibits a total harmonic distortion of -45 dB, dynamic range of more than 65 dB, and beamforming imperfection of less than -50 dB using a 100-kHz input signal with peak voltage of 400 mV.

Keywords

CCD image sensors; CMOS analogue integrated circuits; acoustic signal processing; analogue processing circuits; microsensors; piezoelectric transducers; pipeline processing; ultrasonic delay lines; ultrasonic imaging; ultrasonic transducer arrays; 100 kHz; 400 mV; 8 micron; CMOS process; analog beamformer; beamforming imperfection; bucket-brigade devices; delay lines; dynamic range; image sensors; integrated far-field steering scanning; micromachined piezoelectric ultrasonic sensor phased array; on-chip ultrasound beamforming; peak voltage; pipelined delay-sum architecture; total harmonic distortion; ultrasonic imaging systems; Array signal processing; CMOS process; Delay; Dynamic range; Phased arrays; Piezoelectric devices; Prototypes; Sensor arrays; Total harmonic distortion; Ultrasonic imaging;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2003.817603

Filename

1233795