Weak magnetic field pattern detection by CMOS magnetic latch

A CMOS magnetic latch for digital magnetic field detection is reported. It is based on a single split-drain magnetic field-effect transistor with a positive feedback imported by a pair of lateral floating gates. The magnetic latch achieves its maximum magnetic sensitivity when latch-up takes place. A linear equation is used to model the positive feedback and the latch-up process. By imposing a reset-evaluation mechanism, the magnetic latch is evaluated for digital magnetic pattern detection. Experimental results show that the minimum detectable magnetic flux density for the magnetic latch could be down to less than 0.1 mT with low bit error rate.