DocumentCode
795517
Title
Chip-in-the-loop learning algorithm for Boltzmann machine
Author
Klein, J.O. ; Pujol, H. ; Garda, P.
Author_Institution
Inst. d´´Electron. Fondamentale, Univ. de Paris-Sud, Orsay, France
Volume
31
Issue
12
fYear
1995
fDate
6/8/1995 12:00:00 AM
Firstpage
986
Lastpage
988
Abstract
A new algorithm is presented for chip-in-the-loop learning of the synchronous Boltzmann machine, which has two distinct advantages: it allows optimal use of analogue circuit dynamic range, unlike the conventional learning algorithm, and it features a coherent dual weight representation, which improves learning efficiency
Keywords
Boltzmann machines; analogue computer circuits; learning (artificial intelligence); neural chips; analogue circuit; chip-in-the-loop learning algorithm; coherent dual weight representation; dynamic range; learning efficiency; synchronous Boltzmann machine;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19950685
Filename
390982
Link To Document