• DocumentCode
    795834
  • Title

    Linearisation of MOS resistors using capacitive gate voltage averaging

  • Author

    Ramírez-Angulo, J. ; Sawant, M.S. ; Carvajal, R.G. ; López-Martín, A.

  • Author_Institution
    Klispch Sch. of Electr. & Comput. Eng., New Mexico State Univ., Las Cruces, NM, USA
  • Volume
    41
  • Issue
    9
  • fYear
    2005
  • fDate
    4/28/2005 12:00:00 AM
  • Firstpage
    511
  • Lastpage
    512
  • Abstract
    A compact implementation of a scheme to improve linearity of MOS resistors is introduced. It is based on capacitive gate voltage averaging in conjunction with large resistive biasing elements implemented using MOS transistors operating in subthreshold. Experimental results from a test chip in 0.5 μm CMOS technology are shown that verify the proposed technique.
  • Keywords
    CMOS integrated circuits; MIS devices; linearisation techniques; resistors; 0.5 micron; CMOS technology; MOS resistors; MOS transistor; capacitive gate voltage averaging; resistive biasing elements;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:20050565
  • Filename
    1426553
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=795834