Ultra-fast (0.5-μm) CMOS circuits in fully depleted SOI films

Author

Kamgar, Avid ; Hillenius, Steven J. ; Cong, Hong-Ih L. ; Field, R.L. ; Lindenberger, W. Stewart ; Celler, George K. ; Trimble, Lee E. ; Sheng, T.T.

Author_Institution

AT&T Bell Lab., Murray Hill, NJ, USA

Volume

39

Issue

3

fYear

1992

fDate

3/1/1992 12:00:00 AM

Firstpage

640

Lastpage

647

Abstract

CMOS dual-modulus, divide by 128/129, prescaler circuits were built in thin Si films on SIMOX (separation by implantation of oxygen) wafers. They operated at 6.2 GHz, which is 50% faster than control circuits built in bulk Si. Detailed electrical characterization of individual n- and p-channel transistors was performed. The capacitances for the n and p diodes were also measured. Using these data in circuit simulations, it was determined that the gain in speed was primarily due to the decrease in the parasitic capacitances, in particular that of the source/drain junctions. Also measured were the ring-oscillator delay times, with a minimum delay per stage of 34 ps

Keywords

CMOS integrated circuits; integrated logic circuits; scaling circuits; semiconductor-insulator boundaries; 0.5 micron; 34 ps; 6.2 GHz; CMOS circuits; SIMOX; capacitances; circuit simulations; dual-modulus; electrical characterization; fully depleted SOI films; n-channel transistors; p-channel transistors; prescaler circuits; ring-oscillator delay times; source/drain junctions; thin Si films; ultrafast circuits; CMOS process; CMOS technology; Capacitance measurement; Circuits; Delay; Fabrication; Parasitic capacitance; Pollution measurement; Semiconductor films; Silicon on insulator technology;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.123490

Filename

123490