DocumentCode
80484
Title
SEU Hardened Placement and Routing Based on Slack Reduction
Author
SheXiao Xuan ; Li, Ning
Author_Institution
Sch. of Microelectron., Fudan Univ., Shanghai, China
Volume
61
Issue
5
fYear
2014
fDate
Oct. 2014
Firstpage
2741
Lastpage
2744
Abstract
This paper presents an SEU hardened placement and routing scheme targeted at an application specific integrated circuit. The proposed scheme reduces the positive slack so that the incorrect value caused by SEU in a flip-flop is less likely to be captured by a subsequent flip-flop. Experimental results demonstrate that the proposed scheme can not only reduce the SEU susceptibility of traditional non-hardened circuits but also improve the SEU resistance of hardened circuits further.
Keywords
application specific integrated circuits; flip-flops; SEU hardened placement; application specific integrated circuit; positive slack; routing scheme; slack reduction; subsequent flip-flop; traditional nonhardened circuits; Circuit faults; Clocks; Delays; Latches; Routing; Single event upsets; Tunneling magnetoresistance; Hardened by design; placement and routing; radiation effects; single event upset (SEU);
fLanguage
English
Journal_Title
Nuclear Science, IEEE Transactions on
Publisher
ieee
ISSN
0018-9499
Type
jour
DOI
10.1109/TNS.2014.2353853
Filename
6906312
Link To Document