• DocumentCode
    807941
  • Title

    Optimised multiply/accumulate architecture for very high throughput rate digital filters

  • Author

    McGovern, B.P. ; Woods, R.F. ; McAllister, C.

  • Author_Institution
    Dept. of Electr. & Electron. Eng., Queen´´s Univ., Belfast, UK
  • Volume
    31
  • Issue
    14
  • fYear
    1995
  • fDate
    7/6/1995 12:00:00 AM
  • Firstpage
    1135
  • Lastpage
    1136
  • Abstract
    A new modified circuit for implementing high performance IIR filters based on a pipelined multiply-accumulate (MAC) processor is proposed. Clever deployment of latches in the circuit allows the results to be generated once every cycle thereby providing increased performance with reduced size and power consumption over previously designed circuits
  • Keywords
    IIR filters; digital filters; pipeline arithmetic; digital filters; high performance IIR filters; latches; multiply/accumulate architecture; optimised architecture; pipelined multiply-accumulate processor; very high throughput rate;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19950823
  • Filename
    398578
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=807941