A new algorithm for cyclic and pipeline data conversion

Author

Watanabe, Kenzo ; Temes, Gabor C. ; Tagami, Tomohisa

Author_Institution

Res. Inst. of Electron., Shizuoka Univ., Hamamatsu, Japan

Volume

37

Issue

2

fYear

1990

fDate

2/1/1990 12:00:00 AM

Firstpage

249

Lastpage

252

Abstract

An algorithm is proposed for digital-to-analog conversion. The conversion starts with the most significant bit. This algorithm can be implemented using unity-gain buffers and thus permits high-speed data conversion. Switched-capacitor D/A and A/D converter architectures based on this algorithm are described, and experimental results are presented to demonstrate its validity. Error analysis shows that a conversion accuracy of at least 9 b is obtainable with a monolithic implementation. Computer simulations indicate that video-frequency operation may be possible if fine-line CMOS, bipolar, or BiCMOS technology is used

Keywords

analogue-digital conversion; buffer circuits; digital-analogue conversion; monolithic integrated circuits; A/D converter architectures; BiCMOS technology; SC networks; bipolar; conversion accuracy; cyclic data conversion; digital-to-analog conversion; fine-line CMOS; high-speed data conversion; monolithic implementation; most significant bit; pipeline data conversion; unity-gain buffers; video-frequency operation; Computer architecture; Counting circuits; Data conversion; Digital signal processing; Digital-analog conversion; Error analysis; Pipelines; Signal processing algorithms; Switching converters; Voltage;

fLanguage

English

Journal_Title

Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0098-4094

Type

jour

DOI

10.1109/31.45717

Filename

45717