Effect of Topographical and Layout Factors on Gate CD Modeling for MOS Transistor Area

Author

Izawa, Masaru ; Kurihara, Masaru ; Tanaka, Junichi ; Kawai, Kenji ; Yoshifuku, Ryoichi ; Maruyama, Takahiro ; Fujiwara, Nobuo

Author_Institution

Nano-process Res. Dept., Hitachi, Ltd., Kokubunji

Volume

22

Issue

2

fYear

2009

fDate

5/1/2009 12:00:00 AM

Firstpage

290

Lastpage

296

Abstract

The gate critical dimension (CD) variation of ultra-large-scale integrated circuit (ULSI) devices should be reduced to improve the production yield. An examination of the formulation of a gate-CD model for the transistor area, including the static random access memory (SRAM), was conducted taking the topographical and layout effects into account. It was found that the formulation of a gate CD for transistor areas with a root-mean-square error (RMSE) of less than 1 nm was efficient. The coefficients of the shallow-trench-isolation (STI) step height and polycrystalline-silicon (poly-Si) thickness were found to be inversely proportional to the distance between the gate electrodes. It was found that this dependence is related to the reactive-ion-etching (RIE) lag in the etching process.

Keywords

MOSFET; SRAM chips; ULSI; electrodes; elemental semiconductors; etching; silicon; MOS transistor area; Si; gate CD modeling; gate critical dimension variation; gate electrodes; layout effects; polycrystalline silicon thickness; reactive-ion-etching lag; root-mean-square error; shallow-trench-isolation step height; static random access memory; ultralarge-scale integrated circuit devices; Electrodes; Etching; Integrated circuit modeling; Lithography; MOSFETs; Process control; Production; Random access memory; SRAM chips; Semiconductor device modeling; Gate electrode; MOS devices; SRAM; plasma etching; process control; shallow trench isolation;

fLanguage

English

Journal_Title

Semiconductor Manufacturing, IEEE Transactions on

Publisher

ieee

ISSN

0894-6507

Type

jour

DOI

10.1109/TSM.2009.2017639

Filename

4909527