Delay analysis of CMOS gates using modified logical effort model

Author

Kabbani, A. ; Al-Khalili, D. ; Al-Khalili, A.J.

Author_Institution

Dept. of Electr. & Comput. Eng., Ryerson Univ., Toronto, Ont., Canada

Volume

24

Issue

6

fYear

2005

fDate

6/1/2005 12:00:00 AM

Firstpage

937

Lastpage

947

Abstract

In this paper, modified logical effort (MLE) technique is proposed to provide delay estimation for CMOS gates. The model accounts for the behavior of series-connected MOSFET structure (SCMS), the input transition time, and internodal charges. Also, the model takes into account deep submicron effects, such as mobility degradation and velocity saturation. This model exhibits good accuracy when compared with Spectre simulations based on BSIM3v3 model. Using UMC´s 0.13-μm and TSMC´s 0.18-μm technologies, the model has an average error of 4.5% and a maximum error of 15%.

Keywords

CMOS logic circuits; MOSFET circuits; delays; integrated circuit modelling; logic gates; 0.13 micron; 0.18 micron; BSIM3v3 model; CMOS gates; Spectre simulations; deep submicron effects; delay analysis; delay estimation; input transition time; internodal charges; mobility degradation; modified logical effort model; series-connected MOSFET structure; velocity saturation; CMOS logic circuits; CMOS technology; Degradation; Delay; Inverters; Libraries; MOSFET circuits; Parasitic capacitance; Predictive models; Semiconductor device modeling; CMOS; DSM; delay model; logic gates; logical effort;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/TCAD.2005.847892

Filename

1432884