• DocumentCode
    816053
  • Title

    An approach to construct pre-conditioning matrices for block iteration of linear equations

  • Author

    Wang, Ze-Yi ; Wu, Ke-Chih ; Dutton, Robert W.

  • Author_Institution
    Integrated Circuits Lab., Stanford Univ., CA, USA
  • Volume
    11
  • Issue
    11
  • fYear
    1992
  • fDate
    11/1/1992 12:00:00 AM
  • Firstpage
    1334
  • Lastpage
    1343
  • Abstract
    An approximate block elimination (ABE) method for constructing preconditioning matrices in the block iteration of systems of linear equations is presented. Four families of preconditioning matrices based on this approach are identified for solving the 2×2 block equations with the Jacobian resulted from the 3-D one-carrier semiconductor device analysis problem. The fully coupled Newton´s method is used as a test case on a parallel computer, the Intel iPSC/2 hypercube. There are ten different preconditioning transformations including the alternate block factorization (ABF) and the modified singular perturbation (MSP) schemes. The results from computational experiments indicate that eight of these preconditioning matrices significantly extend the convergence region of the block Gauss-Seidel iteration process of Newton steps and five of them speed up the convergence with a factor of up to more than an order of magnitude
  • Keywords
    convergence of numerical methods; equations; iterative methods; mathematics computing; matrix algebra; parallel processing; semiconductor device models; Intel iPSC/2 hypercube; Jacobian; alternate block factorization; approximate block elimination; block Gauss-Seidel iteration process; block iteration; convergence region; fully coupled Newton´s method; linear equations; modified singular perturbation; parallel computer; preconditioning matrices; preconditioning transformations; semiconductor device analysis; Central Processing Unit; Concurrent computing; Convergence; Finite difference methods; Gaussian processes; Jacobian matrices; Laboratories; Nonlinear equations; Semiconductor devices; Testing;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/43.177397
  • Filename
    177397