• DocumentCode
    816083
  • Title

    Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLL

  • Author

    Maneatis, John G. ; Kim, Jaeha ; McClatchie, Iain ; Maxey, Jay ; Shankaradas, Manjusha

  • Author_Institution
    True Circuits Inc., Los Altos, CA, USA
  • Volume
    38
  • Issue
    11
  • fYear
    2003
  • Firstpage
    1795
  • Lastpage
    1803
  • Abstract
    A self-biased phase-locked loop (PLL) uses a sampled feedforward filter network and a multistage inverse-linear programmable current mirror for constant loop dynamics that scale with reference frequency and are independent of multiplication factor, output frequency, process, voltage, and temperature. The PLL achieves a multiplication range of 1-4096 with less than 1.7% output jitter. Fabricated in 0.13-μm CMOS, the area is 0.182mm2 and the supply is 1.5 V.
  • Keywords
    CMOS analogue integrated circuits; application specific integrated circuits; current mirrors; feedforward; phase locked loops; timing jitter; 0.13 micron; 1.5 V; ASICs; CMOS; multiplication range; multistage inverse-linear programmable current mirror; output jitter; reference frequency; sampled feedforward filter network; self-biased phase-locked loop; Application specific integrated circuits; Bandwidth; Clocks; Damping; Filters; Frequency; Jitter; Phase locked loops; Temperature; Voltage;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/JSSC.2003.818298
  • Filename
    1240958
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=816083