Revisited RF Compact Model of Gate Resistance Suitable for High-K/Metal Gate Technology

Author

Dormieu, B. ; Scheer, P. ; Charbuillet, C. ; Jaouen, H. ; Danneville, Frangois

Author_Institution

STMicroelectron., Crolles, France

Volume

60

Issue

1

fYear

2013

fDate

Jan. 2013

Firstpage

13

Lastpage

19

Abstract

State-of-the-art compact models of gate access resistance are investigated and compared with RF measurements for 28-nm high-k/metal gate MOS transistors. This work shows that the usual lumped gate resistance model fails to capture both geometry scaling and voltage dependence observed on silicon. The increasing role of the interface resistance is highlighted, and an improved gate access resistance model is proposed, featuring an encapsulation of the interface resistance component by parasitic capacitances. Theoretical insights and relevance of this new distributed model and associated parameters are also discussed.

Keywords

MOSFET; encapsulation; semiconductor device models; MOS transistors; RF compact model; RF measurements; associated parameters; distributed model; encapsulation; gate access resistance model; geometry scaling; high-k/metal gate technology; interface resistance component; lumped gate resistance model; parasitic capacitances; silicon; size 28 nm; state-of-the-art compact models; theoretical insights; voltage dependence; Capacitance; Electrical resistance measurement; Logic gates; Radio frequency; Resistance; Substrates; Transistors; 28nm; Compact modeling; HKMG; MOS; RF; gate resistance;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/TED.2012.2225146

Filename

6365800