• DocumentCode
    821222
  • Title

    Pipelined recursive filter with minimum order augmentation

  • Author

    Lim, Y.C. ; Liu, Bede

  • Author_Institution
    Dept. of Electr. Eng., Nat. Univ. of Singapore, Singapore
  • Volume
    40
  • Issue
    7
  • fYear
    1992
  • fDate
    7/1/1992 12:00:00 AM
  • Firstpage
    1643
  • Lastpage
    1651
  • Abstract
    Pipelining is an efficient way for improving the average computation speed of an arithmetic processor. However, for an M-stage pipeline, the result of a given operation is available only M clock periods after initiating the computation. In a recursive filter, the computation of y(n) cannot be initiated before the computations of y(n-1) through y(n-N) are completed. H.B. Voelcker and E.E. Hartquist (1970) and P.M.Kogge and H.S. Stone (1973) independently devised augmentation techniques for resolving the dependence problem in the computation of y(n). However, the augmentation required to ensure stability may be excessively high, resulting in a very complex numerator realization. A technique which results in a minimum order augmentation is presented. The complexity of the resulting filter design is very much lower. Various pipelining architectures are presented. It is demonstrated by an example that when compared to the prototype filter, the augmented filter has a lower coefficient sensitivity and better roundoff noise performance
  • Keywords
    digital filters; pipeline processing; digital filters; filter design; lower coefficient sensitivity; minimum order augmentation; pipelined recursive filter; pipelining architectures; roundoff noise; Arithmetic; Circuits; Clocks; Delay; Filters; Latches; Logic; Pipeline processing; Prototypes; Sampling methods;
  • fLanguage
    English
  • Journal_Title
    Signal Processing, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1053-587X
  • Type

    jour

  • DOI
    10.1109/78.143436
  • Filename
    143436