Pipelined recursive modified Euclidean algorithm block for low-complexity, high-speed Reed-Solomon decoder

Author

Lee, H. ; Azam, A.

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. of Connecticut, Storrs, CT, USA

Volume

39

Issue

19

fYear

2003

Firstpage

1371

Lastpage

1372

Abstract

A novel pipelined recursive modified Euclidean (ME) algorithm block for the low-complexity, high-speed Reed-Solomon (RS) decoder is presented. The deeply pipelined recursive structure enables implementation of a significantly low-complexity ME algorithm block with much improved clock frequency. The low-complexity, high-speed RS decoder using the pipelined recursive ME algorithm block has been implemented in 0.13 μm CMOS technology with a supply voltage of 1.1 V. The results show that it has significantly low hardware complexity and a high data processing rate of 6.16 Gbit/s.

Keywords

CMOS digital integrated circuits; Reed-Solomon codes; circuit complexity; decoding; digital signal processing chips; high-speed integrated circuits; pipeline processing; 0.13 micron; 1.1 V; 6.16 Gbit/s; CMOS technology; Reed-Solomon decoder; clock frequency improvement; deeply pipelined recursive structure; high-speed RS decoder; low-complexity RS decoder; modified Euclidean algorithm block; pipelined recursive algorithm block;

fLanguage

English

Journal_Title

Electronics Letters

Publisher

iet

ISSN

0013-5194

Type

jour

DOI

10.1049/el:20030886

Filename

1244148