Comments on "A method of fault simulation based on stem regions

Author

Lee, H.K. ; Ha, Dong Sam

Author_Institution

Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA

Volume

11

Issue

3

fYear

1992

fDate

3/1/1992 12:00:00 AM

Firstpage

407

Lastpage

408

Abstract

For the original article see ibid., vol.9, no.2, p.212-20 (1990). The commenters show a counterexample for the region extraction algorithm given in the above-mentioned work by F. Maamari and J. Rajski. A four-step region extraction algorithm was given to extract the exit lines of each stem. In steps 1 and 2, primary reconvergent gates (PRGs) and secondary reconvergent gates (SRGs) of the stem are identified. In steps 3 and 4, closing reconvergent gates (CRGs) and exit lines are computed. In step 2, the algorithm does not identify some SRGs which could be exit lines of the stem. As a result, the fault simulation may be incorrect for some faults. The commenters show this case using an example circuit.<>

Keywords

circuit analysis computing; combinatorial circuits; digital simulation; fault location; logic testing; fault simulation; reconvergent gates; region extraction algorithm; stem regions; Automatic testing; Benchmark testing; Central Processing Unit; Circuit faults; Circuit simulation; Circuit testing; Fault detection; Fault diagnosis; Redundancy; Very large scale integration;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/43.124428

Filename

124428