Programmable high-performance IIR filter chip

Author

Woods, R.F. ; Floyd, G. ; Wood, K. ; Evans, R. ; McCanny, J.V.

Author_Institution

Inst. of Adv. Microelectron., Queen´´s Univ., Belfast, UK

Volume

142

Issue

3

fYear

1995

fDate

6/1/1995 12:00:00 AM

Firstpage

179

Lastpage

185

Abstract

The paper presents a state-of-the-art commercial demonstrator chip for infinite impulse response (IIR) filtering. The programmable IIR filter chip contains eight multiplier/accumulators that can be configured in one of five different modes to implement up to a 16th-order IIR filter. The multiply-accumulate block is based on a highly regular systolic array architecture and uses a redundant number system to overcome problems of pipelining in the feedback loop. The chip has been designed using the GEC Plessey Semiconductors CLA78000 series gate array, operates on 16-bit two´s complement data and has a clock speed of 30 MHz. Issues such as overflow detection and design for testability have also been addressed and are described

Keywords

IIR filters; digital filters; logic arrays; multiplying circuits; programmable filters; redundant number systems; systolic arrays; 16 bit; 30 MHz; GEC Plessey Semiconductors CLA78000 series; IIR filter chip; clock speed; design for testability; gate array; infinite impulse response; multiplier/accumulators; overflow detection; pipelining; redundant number system; systolic array architecture; two´s complement data;

fLanguage

English

Journal_Title

Circuits, Devices and Systems, IEE Proceedings -

Publisher

iet

ISSN

1350-2409

Type

jour

DOI

10.1049/ip-cds:19951892

Filename

401296