Chip complexity requires signal and power integrity

Author

Matsui, Norio ; Divekar, Dileep ; Orhanovic, Neven ; Wabuka, Hiroshi

Volume

25

Issue

6

fYear

2006

Firstpage

24

Lastpage

29

Abstract

With an increase in operating frequency and the complexity of system on a chip (SOC), it becomes important to consider the noise generated along the signal and power/ground interconnections that leads to malfunction. We have developed a new simulation method for the full chip-level signal and power-integrity analysis. The CAD layout data is converted into SPICE transmission line models considering silicon substrate effects. To remove the limitation of size and complexity of layout data in the real LSI chips, a sectioning method using MOR with super linear solver has been introduced. The proposed method can also be extended to the computation of current/voltage distributions leading to EMI analysis

Keywords

SPICE; circuit CAD; circuit complexity; circuit simulation; integrated circuit design; power integrated circuits; system-on-chip; CAD layout; EMI analysis; SOC; SPICE transmission line model; power-integrity analysis; sectioning method; silicon substrate effect; system-on-chip; Analytical models; Frequency; Noise generators; Power generation; Power system interconnection; Power transmission lines; SPICE; Signal analysis; Signal generators; System-on-a-chip;

fLanguage

English

Journal_Title

Potentials, IEEE

Publisher

ieee

ISSN

0278-6648

Type

jour

DOI

10.1109/P-M.2006.248053

Filename

4013572