A 100-MHz 8-mW ROM-less quadrature direct digital frequency synthesizer

Author

Mohieldin, Ahmed Nader ; Emira, Ahmed A. ; Sánchez-Sinencio, Edgar

Author_Institution

Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA

Volume

37

Issue

10

fYear

2002

fDate

10/1/2002 12:00:00 AM

Firstpage

1235

Lastpage

1243

Abstract

A low-power quadrature direct digital frequency synthesizer (DDFS) is presented. Piecewise linear approximation is used to avoid using a ROM look-up table to store the sine values as in a conventional DDFS. Significant saving in power consumption, due to the elimination of the ROM, renders the design more suitable for portable wireless communication applications. To demonstrate the proposed technique, a quadrature DDFS has been implemented using 0.5-μm CMOS process and occupies an active area of 1.4 mm². It consumes 8 mW at 100 MHz and operates from a single 2.7-V supply. The spurious-free dynamic range is better than 59 dBc at low synthesized frequencies and the frequency resolution is 1.5 kHz.

Keywords

CMOS digital integrated circuits; digital-analogue conversion; direct digital synthesis; high-speed integrated circuits; low-power electronics; mobile radio; piecewise linear techniques; 0.5 micron; 100 MHz; 2.7 V; 8 mW; CMOS process; ROM-less quadrature DDS; direct digital frequency synthesizer; low-power synthesizer; piecewise linear approximation; portable wireless communication applications; quadrature DDFS; switched weighted-sum block; Frequency shift keying; Frequency synthesizers; Phase locked loops; Piecewise linear approximation; Quantization; Read only memory; Signal resolution; Table lookup; Voltage-controlled oscillators; Wireless communication;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2002.803008

Filename

1035937