Error cancellation technique for capacitor arrays in A/D and D/A converters

Author

Tröster, Gerhard ; Herbst, Dieter

Author_Institution

Telefunken Electron. GmbH, Heilbronn, West Germany

Volume

35

Issue

6

fYear

1988

fDate

6/1/1988 12:00:00 AM

Firstpage

749

Lastpage

751

Abstract

An error-correction technique for monolithic high-speed A/D and D/A converters, based on binary weighted capacitor arrays, is introduced. Each capacitor in the array has its individual calibration capacitor and voltage source. The calibration voltages are generated by resistive DACs. An N-bit converter requires N additional capacitors, N analog switching matrices, and N bytes of memory space. The error-acquisition technique and practical design considerations are presented

Keywords

analogue-digital conversion; calibration; digital-analogue conversion; error correction; field effect integrated circuits; A/D convertors; ADC; D/A converters; DAC; MOS type; analog switching matrices; binary weighted capacitor arrays; calibration capacitor; calibration voltages; error-acquisition technique; error-correction technique; monolithic high-speed convertors; voltage source; Calibration; Error correction; Linearity; MOS capacitors; Matrix converters; Switches; Switching circuits; Switching converters; Very large scale integration; Voltage;

fLanguage

English

Journal_Title

Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0098-4094

Type

jour

DOI

10.1109/31.1814

Filename

1814