• DocumentCode
    834879
  • Title

    Simple optimising methodology for static frequency divider design

  • Author

    Dong, P. ; Hayes-Gill, B. ; Harrison, I.

  • Author_Institution
    Sch. of Electr. & Electron. Eng., Univ. of Nottingham
  • Volume
    42
  • Issue
    22
  • fYear
    2006
  • Firstpage
    1267
  • Lastpage
    1268
  • Abstract
    An optimising method to improve the speed of a source-coupled-logic static frequency divider is presented. A piecewise linear transistor model is applied to simplify the large-signal analysis. The optimised circuit parameters can be quickly estimated from the analysis result. The simulation and measurement results on a 0.35 mum CMOS process have been used to demonstrate this optimisation method
  • Keywords
    CMOS logic circuits; circuit optimisation; frequency dividers; piecewise linear techniques; 0.35 micron; CMOS process; large-signal analysis; optimising methodology; piecewise linear transistor model; source-coupled-logic; static frequency divider;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:20062346
  • Filename
    4015908
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=834879