Symbolic layout compaction under conditional design rules

Author

Cheng, Chung-Kuan ; Deng, Xiaotie ; Liao, Yuh-Zen ; Yao, So-Zen

Author_Institution

Dept. of Comput. Sci. & Eng., California Univ., San Diego, CA, USA

Volume

11

Issue

4

fYear

1992

fDate

4/1/1992 12:00:00 AM

Firstpage

475

Lastpage

486

Abstract

The compaction of IC layouts subjected to conditional spacing rules in multiple-level metal technology is addressed. The constraints imposed by conditional rules make the automatic compaction of layout much more difficult than when the usual minimum separation rules are applied. To solve the problem, each conditional spacing rule is formulated with a set of arcs in the constraint graph representation. It is proven that finding the optimal solution under one bridge rule is NP-complete. A graph-theory method of compaction which, by reducing the problem size, can efficiently obtain an optimal solution is proposed

Keywords

circuit layout CAD; graph theory; integrated circuit technology; IC layouts; NP-complete; conditional design rules; conditional spacing rules; constraint graph representation; graph-theory method; multiple-level metal technology; optimal solution; symbolic layout compaction; Application specific integrated circuits; Bridge circuits; Circuit optimization; Compaction; Fabrication; Integrated circuit layout; Paper technology; Routing; Textile industry; Topology;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/43.125095

Filename

125095