Effect of Silicon Thickness on Contact-Etch-Stop-Layer-Induced Silicon/Buried-Oxide Interface Stress for Partially Depleted SOI

Author

Lin, Chien-Ting ; Fang, Yean-Kuen ; Yeh, Wen-Kuan ; Lee, Tung-Hsing ; Chen, Ming-Shing ; Hsu, Che-Hua ; Chen, Liang-Wei ; Cheng, Li-Wei ; Ma, Mike

Author_Institution

Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan

Volume

27

Issue

12

fYear

2006

Firstpage

963

Lastpage

965

Abstract

In this letter, based on both experimental investigations and simulation confirmation, it was found that a strained contact etch stop layer over the thin silicon layer of a partially depleted silicon-on-insulator (PD-SOI) will induce high stress on the buried-oxide/silicon interface. Additionally, the interface stress increases with decrease of silicon thickness T_SI, thus enhancing the current of the MOSFET, e.g., as T_SI shrinks from 90 to 50 nm, current enhancement for PD-SOI n-channel MOS increased from 7% to 12% due to the increase of interface stress. The results are expected to be more significant for devices with thinner T_SI such as fully depleted silicon-on-insulator and multigate devices

Keywords

MOSFET; silicon-on-insulator; stress effects; MOSFET; PD-SOI; buried-oxide/silicon interface; interface stress; multigate devices; partially depleted silicon-on-insulator; silicon thickness; strain engineering; strained contact etch stop layer; thin silicon layer; Automotive engineering; CMOS technology; Capacitive sensors; Etching; MOS devices; Microelectronics; Optimized production technology; Power engineering and energy; Silicon on insulator technology; Stress; Contact etch stop layer (CESL) buried oxide (BOX); interface stress; partially depleted silicon-on-insulator (PD-SOI); strain engineering;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/LED.2006.886715

Filename

4016193