Analysis of Multilayered Microelectronic Packaging Under Thermal Gradient Loading

An accurate estimation of interfacial and axial stresses in multilayered structures is important in the design process of microelectronic packaging because these stresses drive the failure modes in the package. During manufacturing, microelectronic packaging devices usually suffer from severe thermal gradients. Design engineers often simplify the thermal gradient case as an isothermal loading case by averaging the temperature of the top and bottom of the microelectronic packaging device. Such simplification usually underestimates the stress level in the devices. With the analytical model presented in this paper, the stresses in multilayered microelectronic packaging devices subjected to thermal gradient loading can easily be predicted. It is shown that ignoring the thermal gradient in the package leads to underestimation of stresses