Register-transfer-level power estimation based on technology decomposition

A new register-transfer level power estimation technique based on technology decomposition is presented. The power dissipation is estimated by predicting the node distribution, capacitance distribution and entropy distribution of the minimum area implementation of a given Boolean functional description. This approach makes it possible to capture the structural information of a circuit without actual gate-level implementation. Compared to the exact values of power obtained from a logic synthesis system, the estimator produces an average percentage error of 7.5%, which is a significant improvement over previous techniques