Clock-Logic Domino Circuits for High-Speed and Energy-Efficient Microprocessor Pipelines

We present a design methodology for synchronous single-rail domino logic circuits, where inverting and nonmonotonic logic functions can be integrated into a pipeline with almost zero overhead relative to classic domino counterparts. This logic family, called clock-logic (CL) domino, is functionally complete while tolerating skew and minimizing the number of clock phases that must be distributed. Simulation results for a CL domino algorithmic logic unit (ALU) at 1 GHz under high skew conditions, shows a power reduction of 41% over the same ALU implemented in dual-rail skew-tolerant domino logic. This power reduction incurs no performance penalty over dual-rail techniques, although in some cases additional design effort is required