Efficient Low-Temperature Data Retention Lifetime Prediction for Split-Gate Flash Memories Using a Voltage Acceleration Methodology

In developing a fast statistical testing methodology to predict the postcycling low-temperature data-retention lifetime of split-gate Flash memories, word-line stress is used to accelerate the charge-gain effect responsible for bit-cell-current reduction among the tail-bits. To find out the voltage dependence on data-retention lifetime, various word-line stress voltages are performed to enhance the charge-gain effect of the erase-state cells. At an accelerated state, word-line stress lifetime tests can be completed within a much shorter test period and still provide accurate lifetime prediction for embedded Flash-memory products