DocumentCode
84214
Title
SEGR in SiO 
–Si 
N 
Author
Javanainen, Arto ; Ferlet-Cavrois, Veronique ; Bosser, Alexandre ; Jaatinen, Jukka ; Kettunen, Heikki ; Muschitiello, Michele ; Pintacuda, Francesco ; Rossi, Mattia ; Schwank, James R. ; Shaneyfelt, Marty R. ; Virtanen, Ari
Author_Institution
Dept. of Phys., Univ. of Jyvaskyla, Jyväskylä, Finland
Volume
61
Issue
4
fYear
2014
fDate
Aug. 2014
Firstpage
1902
Lastpage
1908
Abstract
This paper presents experimental Single Event Gate Rupture (SEGR) data for Metal-Insulator-Semiconductor (MIS) devices, where the gate dielectrics are made of stacked SiO2-Si3N4 structures. A semi-empirical model for predicting the critical gate voltage in these structures under heavy-ion exposure is first proposed. Then interrelationship between SEGR cross-section and heavy-ion induced energy deposition probability in thin dielectric layers is discussed. Qualitative connection between the energy deposition in the dielectric and the SEGR is proposed.
Keywords
MIS devices; dielectric materials; probability; semiconductor device models; silicon compounds; SiO2-Si3N4; gate dielectrics; heavy-ion exposure; heavy-ion induced energy deposition probability; metal-insulator-semiconductor devices; qualitative connection; semi-empirical model; thin dielectric layers; Dielectrics; Electric breakdown; Ions; Logic gates; Silicon; Threshold voltage; $hbox {Si}_{3}hbox {N}_{4}$ ; $hbox {SiO}_2$
fLanguage
English
Journal_Title
Nuclear Science, IEEE Transactions on
Publisher
ieee
ISSN
0018-9499
Type
jour
DOI
10.1109/TNS.2014.2303493
Filename
6800102
Link To Document