Equalization and clock recovery for a 2.5-10-Gb/s 2-PAM/4-PAM backplane transceiver cell

Author

Zerbe, Jared L. ; Werner, Carl W. ; Stojanovic, Vladimir ; Chen, Fred ; Wei, Jason ; Tsang, Grace ; Kim, Dennis ; Stonecypher, William F. ; Ho, Andrew ; Thrush, Timothy P. ; Kollipara, Ravi T. ; Horowitz, Mark A. ; Donnelly, Kevin S.

Author_Institution

Rambus Inc., Los Altos, CA, USA

Volume

38

Issue

12

fYear

2003

Firstpage

2121

Lastpage

2130

Abstract

A folded multitap transmitter equalizer and multitap receiver equalizer counteract the losses and reflections present in the backplane environment. A flexible 2-PAM/4-PAM clock data recovery circuit uses select transitions for receive clock recovery. Bit-error rate less than 10^-15 and power equal to 40 mW/Gb/s has been measured when operating over a 20-in backplane with two connectors at 10 Gb/s.

Keywords

adaptive equalisers; clocks; decision feedback equalisers; error statistics; transceivers; 2.5 to 10 Gbit/s; 2.5-10-Gb/s 2-PAM/4-PAM backplane transceiver cell; 40 mW; SerDes; adaptive equalizers; backplane environment; bit-error rate; decision feedback equalizers; equalization; flexible 2-PAM/4-PAM clock data recovery circuit; folded multitap transmitter equalizer; multilevel systems; multitap receiver equalizer; pulse amplitude modulation; receive clock recovery; select transitions; serial links; Backplanes; Bit error rate; Clocks; Equalizers; Flexible printed circuits; Power measurement; Propagation losses; Reflection; Transceivers; Transmitters;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2003.818572

Filename

1253859