Logic testability of defective floating gate CMOS latches

The behaviour of a defective CMOS latch cell with floating gate defects is analysed in order to investigate the detection of these defects by logic testing. A large number (40%) of the defects will never be detectable by logic testing. Some of the remaining floating gate defects are also undetectable by logic testing, depending on their defect topologies. The need for other test methods such as I_DDQ or delay testing is discussed.